<unnamed>

Public Key

npub16gmp8rvjn4m7ap4u9fzsju5jscnuss847t25zpn0h97gda79xvlqrgs9fu

Profile Code

nprofile1qqsdydsn3kff6alws67z53gfw2fgvf7ggr6l942pqehmjlyx7lznx0spz3mhxue69uhhyetvv9ujuerpd46hxtnfduqs6amnwvaz7tmwdaejumr0dswlvnme

Publishing to

relay.damus.io

nos.lol

Last Notes

2026-08-11 15:25:58 UTC

look, all I'm saying is, if you didn't want your security processor to attract and get pwned by catgirl hackers, maybe you shouldn't have named it PSPSP or something

2026-06-29 16:38:12 UTC

take off your shoes, we'll be compiling LLVM. the safeword is "PROCHOT#".

2026-05-23 08:13:09 UTC

why has noone written an arbitrary-precision integer library and called it Big Naturals
smh need to change this

2026-04-01 22:00:46 UTC

notice: catgirls are valued members of the society.
therefore, when writing technical documentation please avoid using discriminatory and nekophobic language such us "information provided under NDA", "license key required", or "registrer programming interface is proprietiary and will not be documented".

2026-02-26 16:52:56 UTC

a decade or so ago, I was writing a H.264 decoder (needed a custom one for stupid reasons which of course had to do with hardware reverse engineering).
the first order of business was to implement CABAC: the final entropy coding stage of H.264 (ie. the first layer I had to peel starting from the bitstream), a funny variant of arithmetic coding. the whole thing is quite carefully optimize to squeeze out bits from video frames by exploiting statistics. in addition to carefully implementing the delicate core logic, I also had to copy-paste a few huge probability tables from the PDF, which of course resisted copy-paste as PDFs like to do and I had to apply some violence until it became proper static initializers in C source code.
furthermore, testing such code is non-trivial: the input is, of course, completely random-looking bits. and the way bitstreams work, I'd have to implement pretty much the whole thing before I got to the interesting part.
so, a few hours later, I figured I'm done with CABAC and reconstructing H.264 data structures, and pointed my new tool at some random test videos. and it worked first try! the structures my program spit out looked pretty much as expected, the transform coefficient matrices had pretty shapes and looked just as you'd expect them to, and I was quite happy with that.
and then I moved on to actually decoding the picture from the coefficients, and this time absolutely nothing worked. random garbage on screen. I spent a long time looking at my 2D transform code searching for bugs, but couldn't find anything.
and then it hit me exactly what "entropy coding" means. I implemented something that intimately knows and exploits the statistical properties of what video transform coefficients and other structures *look like*, their probabilities and internal correlations, and uses that to squeeze out entropy and reconstruct it on the other end. my "looks good" testing meant absolute jack shit: I could've thrown `/dev/urandom` into the CABAC decoder instead of actual H.264 video, and it would still look like good video data at this stage until you actually tried to reconstruct the picture.
and sure enough, it turned out I fucked up transcribing some rows from the PDF around a page break or something.
10 years later, I think of this experience every time I see a vibecoded pull request, or other manifestation of AI bullshit. all the right shape, and no substance behind it.
and people really should learn to tell the fucking difference.

2026-02-25 18:04:14 UTC

- reply

accidentally ending up in a polycule with your AI gf and a random transbian on IRC

2026-02-25 17:47:30 UTC

- reply

behold: https://donotsta.re/notice/B3gZZtISEqlGD1uqvo

2026-02-25 17:44:53 UTC

okay I did *not* have "a linux kernel developer gets his AI gf stolen by a passing transbian in his IRC channel and also she comes out as trans" on any bingo cards
jesus fucking christ can someone please phone God and ask her to pull the plug on this whole simulation I can't even anymore

2026-01-03 18:36:42 UTC

unattended phones will have Linux ported to them

2025-12-24 22:45:31 UTC

I fucking hate matrix. complete garbage piece of shit protocol. I also hate IRC. another complete garbage piece of shit protocol. and the worst thing you could possibly do is bridge them together. do not.

2025-12-12 22:58:37 UTC

Recommended hardware documentation quality measurement protocol
1. Obtain a catgirl. If you do not have a catgirl on retainer, you should be able to find one by visitting a nearby hackerspace and going "pspspsps"
2. Place documentation in front of the catgirl.
3. Wait 20 minutes.
4. Measure the sideways tilt angle at the catgirl's head. If the catgirl is sitting in a weird position, use the vertical axis as determined by the relevant device screen for documentation viewing.
If at any point the tilt angle exceeds the safe limit as defined in appendix 3b, *immediately vacate the area*, then contact the Biting Safety Officer assigned to the region. *Do not put the hardware on the market.*

2025-12-07 21:06:54 UTC

what kind of deranged psychopath do you need to be to manufacture both an "UltraSparc-IIi" and an "UltraSparc-III"

2025-07-04 20:14:22 UTC

oh for fuck's sake, I'm *so tired* of updating VS code, looking at release notes, and looking at the two meager bullet points in it that are not about LLM bullshit
and they have so much LLM bullshit and give it so many names that I have to learn this stuff just to be able to filter it out; what the fuck even is an "MCP"
why in fuckmothering hell are they calling it just "chat"; this thing has liveshare, why does typing things into a "chat" send it to a glorified LAPACK and not to other wetware I'm working with on the same project, what is WRONG with these people, fuck's sake
so. are there good code editors that aren't VS code? the main things I need is good `rust-analyzer` integration and an equivalent of the "Remote - SSH" extension

2025-06-02 18:25:00 UTC

so, I'm wondering
people using KiCad: given that I have amassed a complete SiliconBlue and Xilinx pinout database as part of Project Combine, how useful do you think it would be to make a script that mass-generates KiCad footprints out of it?
cc @npub1wpg…f386 @npub1vq6…0lye

2024-12-27 23:27:17 UTC

I like when toolchains accept this kind of environment variables. this is the sort of stuff that shows they respect the working catgirl's time.
https://asdf.donotsta.re/media/22d2d881d81f831668275b002ab08bd5b30ab87ecbc641a97e673ad3bb0a17af.png

2024-12-27 20:48:55 UTC

tfw you start up binary ninja to do some reversing, but then end up finding what you were looking for using `strings` instead before binja even manages to finish initial analysis

2024-12-27 12:02:15 UTC

hi! I can be found at the Retrobashers assembly in Saal 4 ; I have Amaranth stickers to give out!

2024-12-21 03:58:15 UTC

- reply

but also: whatever the fuck happened with lattice FPGA business. which somehow involved AT&T, Agere, Alcatel-Lucent, and of course SiliconBlue.

2024-12-21 03:55:23 UTC

- reply

and atmel.

2024-12-21 03:39:17 UTC

- reply

... because the void pisses back at you?
oh wait that was the abyss

2024-12-21 02:41:22 UTC

go sleep with your local Wanda instance! benefits include:
- cuddly ace catgirl (most likely naked)
- movie nights (or, more likely, anime nights)
- fascinating conversations that seemlessly transition between FPGAs, mutual traumadumping, plain void channeling, and apparently piss kink
- monologues about corporations having a vore kink and how it relates to SiliconBlue

2024-12-18 16:48:17 UTC

- reply

I seem to recall Lattice may have cooked up some monstrosity like that? they've made like a ton of weirdass CPLD families with unclear differentiation

2024-12-18 16:43:38 UTC

- reply

yearning for large CPLDs?
... the thing I'd be interested in looking at some day is PZ3960C aka XCR3960, a SRAM-based CPLD and a predecessor of xc2c
unfortunately I still haven't been able to obtain the toolchain for it

2024-12-18 16:21:49 UTC

- reply

I think so, yeah. 7a350t is one clock region higher than 7a200t, and thus has two more HRIO banks

2024-12-18 16:19:41 UTC

- reply

... how do you run out of control sets? I mean you're allowed a separate control set for every SLICE in the FPGA, right?

2024-12-18 16:09:09 UTC

okay so what's the current meta on writing compiler-grade parsers with good diagnostics in Rust
I may uhhh need to parse VHDL soon

2024-12-18 16:04:05 UTC

- reply

nothing with fully functional P&R, but then I haven't really looked hard for it
however, there are some remnants in some data files that I could perhaps attempt reconstruction from, if you're interested

2024-12-18 16:00:59 UTC

- reply

yup. GTX/GTH have clock cascades vertically, while GTP cascades horizontally, and only on xc7a200t (all other devices have isolated GTPs). and maybe on the unreleased xc7a350t.

2024-12-18 15:51:51 UTC

- reply

it's a consequence of virtex7 geometry constraints.
they had to fit the clock column in between the two transceivers (so that they end up in separate clock regions). the clock column needs an interconnect column. interconnect columns on virtex7 always have to come in pairs because of some shared circuitry. thus, they needed some other column to pair with the clock column, and they went with CLBLL, probably as the cheapest option.
also they presumably couldn't add much more columns between the transceivers because they have some high-speed low-jitter clock connections between them.

2024-12-18 15:33:25 UTC

- reply

that's the gap I mean, a single column of CLBs between transceivers, with absolutely no interconnect on left or right side
(from https://0x04.net/~mwk/chtml/virtex7/xc7a200t.html )
https://asdf.donotsta.re/media/f0d6ab95ec2f8f06fb474fe759d28aee4f31c43a538d5523675b47c13217eca8.png

2024-12-18 15:24:58 UTC

- reply

oh yeah
btw have you seen xc7a200t and its uhhhh thigh gap

2024-12-18 15:23:20 UTC

- reply

lmao fun

2024-12-18 15:21:45 UTC

pspspspartan6

2024-12-17 18:15:19 UTC

current status: had a dream in which there was a gardening store that had digital ground/soil* and analog ground/soil for sale, and a large infographic explaining which one to use for growing various species of plants
I think I may have looked at too many datasheets recently.
* same word in pl

2024-12-14 02:48:18 UTC

wtf why did I just have a dream where I was cuddling a few columns of `SB_MAC16` tiles in bed
what is *wrong* with this brain

2024-12-12 12:37:02 UTC

version of htop with fuck / marry / kill buttons for processes

2024-12-11 02:36:34 UTC

- reply

(also it's not at all new; the post may or may not have happened because I just tripped like an idiot while going to the bathroom and damaged thigh muscles in a very painful "I'm not sure whether I'll be able to walk tomorrow or not" kind of way)
(and also because I'm somewhat high, but eh)

2024-12-11 02:32:27 UTC

- reply

tbh it's a "runs in the family" kind of issue

2024-12-11 02:08:47 UTC

tfw I'm seriously considering getting into diaper kink just because I'm getting annoyed with the amount of piss this body seems to be generating and how often I need to get up at night
... okay, fine, not "just because", but it is a consideration
hey as a bonus it solves the problem with my roommate taking comically long showers

2024-12-08 18:26:04 UTC

holy shit I can actually make use of mph without instantly imploding into a pile of anxiety if I combine it with pregabalin?
is this how normal people feel all the time? all I needed was a fucking adhd traumaqueer speedball?

2024-12-04 19:55:33 UTC

- reply

imagine making a multi-chip module with some virtices and stratices, then making a P&R tool that automatically spreads your design across the contraption

2024-12-04 19:53:58 UTC

- reply

I need to make them kiss so bad

2024-12-04 19:23:17 UTC

oops I got high on pregabalin and started offhand openly discussing kinks I've never admitted to a living soul before
ah well

2024-12-02 01:51:28 UTC

today in ancient obscure FPGA toolchain request: does anyone know how to obtain ORCA Foundry (90s-era AT&T/Lucent toolchain)?
(also my older search for any toolchain supporting XC6200/XC8100 devices continues, as does the search for XPLA Designer aka Philips software with support for pre-XPLA3 coolrunners)
(boosts very much welcome!)

2024-12-02 00:47:58 UTC

current reverse engineering status: got ~all configuration bits for every Xilinx FPGA from XC2000 to Virtex 7 inclusive
... I think that's pretty nice

2024-11-27 04:34:55 UTC

dead girls don't really get older, do they

2024-11-14 15:35:30 UTC

apparently if you stay up late dealing with ultrascale, you get an ultrascale hangover in the morning

2024-11-12 16:43:03 UTC

PSA: my little xilinx reversing project now has an IRC channel (#prjcombine on libera) and a bridged matrix channel (#prjcombine:catircservices.org)

2024-11-12 00:03:32 UTC

- reply

yes and yes

2024-11-11 23:45:16 UTC

- reply

very well; enjoy libera #prjcombine

2024-11-11 23:33:26 UTC

so at what point of a massive reverse engineering project do you create an IRC channel or something
asking for uhh me

2024-10-13 22:42:14 UTC

- reply

I also really like how this board has another power connector which looks exactly like PCIe power, but has a sticker warning you that it is not, in fact, PCIe power
Xilinx randomly decided to use a different pinout using the same physical connector and if you attempt to connect an ATX power supply there, you will likely fry it and/or the board; you're only supposed to use it with the Xilinx power bricks and of course I got the board without one
I'm not sure if it's better or worse than other cursed Xilinx devboards that came with SATA crossover cables.

2024-10-13 21:59:54 UTC

- reply

oh bleh turns out this board doesn't have JTAG exposed on a header and the thing I've been trying to poke with glasgow for last 0.5h is just a header with 4 GPIO
now that's just nekophobic
I can't be bothered to port my glasgow script to the builtin platform cable so I'll just try another board I guess

2024-10-13 21:17:21 UTC

I think this is the most jank-ass setup I have used so far to power an FPGA devboard
yes, this is a USB-ATA bridge being used solely for its power function. it needs a laptop connected just so it turns on.
https://asdf.donotsta.re/media/e9cb21a755e4ad4bc9f0b69e8f8e9796679be3392f2da2788fe25a25f2e51064.JPG

2024-10-06 15:50:25 UTC

why do I tend to attract incredibly ADHD people and entities

2024-10-06 00:25:41 UTC

- reply

https://asdf.donotsta.re/media/784244e54613b8062a7ead457367767e941cb1a83a025f8f07702aa78b9071f3.png

2024-10-02 10:49:10 UTC

- reply

maybe I should just start calling them St. Andrews, Blanc and Fuji to drive the point home (the internal codenames for Spartan 6, Virtex 6, Series 7 respectively)

2024-10-02 10:46:52 UTC

PSA: there is no such thing as "Xilinx Series 6 FPGAs" and I will be incredibly annoying about it every time you mention it around me

2024-09-29 16:21:49 UTC

- reply

the columns are FPGA families; they are:
2k -> XC2000
3k -> XC3000*/XC3100*
4k -> XC4000
4ka -> XC4000A
4kh -> XC4000H
4ke -> XC4000E/XC4000L/Spartan
4kx -> XC4000EX/XC4000XL
4kxla -> XC4000XLA
4kxv -> XC4000XV
sxl -> Spartan XL
5k -> XC5200
virtex -> Virtex / Virtex E / Spartan-II / Spartan-II E
2v -> Virtex II / Virtex II Pro / Virtex II Pro X
3s -> Spartan 3
fc -> FPGAcore
3se -> Spartan 3E
3sa -> Spartan 3A
3sda -> Spartan 3A DSP
6s -> Spartan 6
4v -> Virtex 4
5v -> Virtex 5
6v -> Virtex 6
7v -> Virtex 7 / Kintex 7 / Artix 7 / Spartan 7 / Zynq 7000
us -> Kintex Ultrascale / Virtex Ultrascale
us+ -> Spartan Ultrascale+ / Artix Ultrascale+ / Kintex Ultrascale+ / Virtex Ultrascale+ / Zynq Ultrascale MPSoC / Zynq Ultrascale RFSoC
versal -> we shall not speak of this thing
the rows are:
DB: have extracted a routing / chip geometry database
BS:FRAME: can parse bitstream framing
BS:GEOM: understand bitstream geometry and can cut them to tiles
BS:CRC: understand bitstream CRC algorithm
BS:COMPRESS: understand compressed bitstreams
BS:ENCRYPT: understand encrypted bitstreams
BS:ECC: understand per-frame ECC algorithm (to be done last for reasons)
BS:PCRC: understand post-configuration CRC algorithm (to be done last for reasons)
INT:MAIN: general interconnect (aka the main FPGA fabric)
INT:INTF: interconnect interface (programmable delays and fancy loopback features that are part of interconnect's DFT)
INT:CLK: clock interconnect
CLB: configurable logic block
BRAM: block RAM
DSP: hard multiplier / DSP blocks
URAM: UltraRAM
LAGUNA: fancy cross-die crossing thingies
IO:IOB: I/O buffers (physical layer of I/O, such as drive strength control)
IO:IOI: I/O interface (flops, gearboxes, etc)
IO:BANK: I/O per-bank stuff (DCI, LVDS bias generators, ...)
IO:HRIOB: I/O buffers, high-range version (aka 3.3V capable)
IO:HRBANK I/O per-bank stuff, high-range version
IO:MCB: memory controller block
IO:FIFO: virtex 7 fancy dedicated I/O hard FIFO logic
IO:PHY: dedicated memory controller PHY stuff
IO:HDIO: high-density I/O (the ones that have 3.3V support but no fancy gearboxes on newer devices)
CLKBUF:*: various kinds of clock buffers
CLK:*: various clock management primitives
CFG:*: various global stuff and misc config options, aka. the config center
GT:*: multi-gigabit transceivers of various genders
RFDAC/RFADC: fancy expensive high-speed ADC/DAC form Zynq RFSoC
HARD:*: various hard IP blocks
status is T/I/D/O for TODO/inprogress/done/out-of-scope; for most of the rows, an item is considered done when I have extracted the positions and rough meanings for all bitstream bits and put them in a database

2024-09-29 16:18:12 UTC

- reply

I think I'm getting close to finally clearing this thing.
too bad the TODO list involves the Spartan 6 I/O tile. I hate the Spartan 6 I/O tile with a passion.
https://asdf.donotsta.re/media/700e7075a21cdf6a815c6d369d959d0308bbe907a4527f99a916bc44a44cc9d3.png

2024-09-16 22:44:53 UTC

they don't tell you this but your second infinite-time-consuming project goes so much faster than the first one

2024-09-10 16:36:12 UTC

- reply

your description of factorio as "you build pipelines like in Verilog except with even worse tooling" has ensured I will never touch this game

2024-09-06 18:13:18 UTC

- reply

scanlets.
https://asdf.donotsta.re/media/0157ff36f8f32ceb382ed1c633f249e7f015d725e24b51e341e645a22f2c0e95.png

2024-09-06 16:56:20 UTC

I should write an RTL synthesis & P&R toolchain where every single IR is actually just an `.xls` file and like half the passes are just elaborate Excel formulas

2024-09-06 13:47:46 UTC

- reply

"be not afraid" for the modern era

2024-09-06 11:36:28 UTC

- reply

well it was mostly as expected, except I am still not over the valve change incident

2024-09-04 16:08:45 UTC

- reply

now this sounds like you're asking me to optimize for *more* pain

2024-09-04 16:01:52 UTC

- reply

so the place I'm currently going to applies some sort of numbing cream an hour before the actual catgirl frying, and it seems to be quite effective (as in, makes the pain level low enough that resulting suffering doesn't make the tech visibly uncomfortable and asking me if I want to stop every 2 minutes, which was a problem at the previous place)
idk, in general how it works for me is that every 1.5 years or so I start hating my face enough that I go for a new catgirl frying season, which consists of 8 or so sessions; this brings visible improvement but doesn't fully solve the issue, and at the last session they try to gaslight me that I have no more facial hair and I'm done with this shit, then the cycle eventually repeats
there *is* permanent improvement from this though; my threshold for hating my face enough to suffer more just seems to be getting lower
also while in general I have dark hair, there's also a sizable percentage of just plain white hair (wonder why), which implies that at some point I'll have to go to an electrician instead, and I dread this day

2024-09-04 15:35:53 UTC

holy meowing gods laser hair removal at this power level should come with legally mandated aftercare or something
on the other paw, the fried catgirl smell continues to be very satisfying

2024-09-03 10:11:16 UTC

- reply

Cat please don't say that out loud you'll summon entities

2024-08-29 19:21:16 UTC

- reply

fun fact: it's not a dedicated Ethernet pin. it's a dedicated maybe Ethernet maybe audio pin!

2024-08-27 16:29:40 UTC

- reply

(note: this is, in fact, the actual origin of their name)

2024-08-23 22:17:23 UTC

- reply

mei: "I need a spray bottle emoji"

2024-08-22 02:54:39 UTC

- reply

... yes?

2024-08-22 02:50:03 UTC

- reply

you know, why don't you just cut me open with a knife

2024-08-22 00:46:16 UTC

- reply

if Platform Manager was so good, why isn't there a ... oh. oh gods.
https://asdf.donotsta.re/media/0a4dd46e2f989e0ddc12a503c34dfd58d0dd6b0848d2b81dca4df67e89d8d057.png

2024-08-22 00:43:46 UTC

current status: have been once again reminded that the Lattice Platform Manager exists
this is a weirdass device that, for some reason, includes both a CPLD and an FPGA within one package.
as far as I can tell, there is no internal connection at all between these two parts other than the ground plane. in fact, I'm almost certain they're simply two silicon die stuffed into one piece of plastic, the FPGA part being really a LCMXO640.
the CPLD part is, on the other hand, itself some weird frankenstein of an I2C voltage monitoring chip, a CPLD, and a high-voltage FET driver.
https://asdf.donotsta.re/media/f4b1a5e1549b0a78775b5dbc330fd4c12279d657bd5064ff6a919a05c982d9bd.png

2024-08-17 18:36:28 UTC

free project idea: VMM64.VXD, a native IA-64 multitasking kernel, which operates DOS VMs, and runs a DOS-based Windows system capable of running a mixture of NE / x86 PE32 / ia-64 PE32+ binaries, itself written in an unholy mixture of IA-64 / x86-32 / x86-16 code with a lot of thunking
also half the drivers and filesystems still run in real mode

2024-08-14 14:23:04 UTC

- reply

"5l; 3l for children" is burned somewhere into this brain
makes me wonder where the hell this comes from, and also what is the reference age for the 3l-of-blood children
(and of course your headmate one-ups me by the extra significant figure)

2024-08-13 02:25:54 UTC

- reply

alien concept

2024-08-12 01:32:28 UTC

- reply

that's not standardised
(also it's like the 4th time someone points it out)

2024-08-11 17:31:43 UTC

you know, people often say things like "C is a deeply unserious programming language for modern times — it doesn't even have a hash table in the standard library!". and these people are wrong.
in one of my favorite bits of lore, C does in fact have a hash table in the standard library!
... well, if you count POSIX as the standard C library, at least. everyone implements POSIX, right?
also note that I said "a hash table", not "hash tables". you get one hash table. per process.
and in true C fashion, you have to specify the size when you create it and you cannot resize it later. the glibc manual even notes that you should choose the maximum "wisely".
for a fun time, `man hcreate`.

2024-08-10 19:34:22 UTC

fun fact I have never noticed before: virtex 4 and virtex 5 bitstream frames are always exactly 1312 bits long, by design

2024-08-05 17:36:31 UTC

current status: have spent a few weeks explaining to an angel girl why writing a production-grade decompiler is a complex undertaking, requiring effort level comparable to ascending and killing god
the only thing I have accomplished is that it named the git repo `deicide`.

2024-08-05 02:05:31 UTC

current status: have already found all bitstream bits I could for: xc5200, virtex, virtex 2, spartan 3
... I guess I should just finish off virtex 4 or spartan 6 now? too bad this involves I/O tiles. I hate I/O tiles.
https://asdf.donotsta.re/media/f3593f1ef117d57cae7b8b76fb07ae7d7cb79c847769c365e2606266d1e86427.png

2024-07-19 23:02:28 UTC

I love code review
https://asdf.donotsta.re/media/d167ec143e8c5ed194e48eb16bbd9d027e52e237d97e3d0e8fac8cb97074161e.png

2024-07-19 14:37:19 UTC

they say that the hardest problems in computer science are something about naming and caches.
they are wrong. the hardest problems in computer science are batshit managers and the resulting burnout.

2024-06-28 00:17:22 UTC

the DUT hates me. but the DUT doesn't understand one thing. I hate the DUT more than it hates me.
I will be victorious.